1. Field of the Invention
The present invention relates generally to the field of semiconductor packaging and, more particularly, to a flip-chip ball grid array (BGA) package with reduced thermal stress during thermal stress cycles.
2. Description of the Prior Art
High performance microelectronic devices often use solder balls or solder bumps for electrically and mechanically interconnection to other microelectronic devices. For instance, a very large scale integration (VLSI) chip may be connected to a circuit board or other next level packaging substrate by using solder balls or solder bumps. This connection technology is also referred to as “flip-chip” technology. Flip-chip technology uses area array connection and includes reflowing a body of solder onto a bonding pad to form a solder bump, so as to electrically connect an IC die to a packaging substrate. Electrical performance is effectively improved due to a shorter connection pass.
FIG. 1 is a schematic diagram of a prior art ball grid array (BGA) package. As shown in FIG. 1, BGA package 10 comprises a silicon chip 12 and a plastic substrate 18. The silicon chip 12 comprises a plurality of solder bump pads 14 respectively connecting to the corresponding solder bumps 16. The solder bump pads 14 connect to the plastic substrate 18 via the solder bumps 16. A gap between the silicon chip 12 and the plastic substrate 18 is filled with an underfill layer 20. The underfill layer 20 is used to provide better mechanical strength and adhesion during the stress cycles, however, the weak point is still in the chip's corners.
Drawbacks of the prior art package include interface delamination and corner bump cracking, which often occur at chip's corner during thermal stress test. It is believed that such delamination or cracking defects are caused by the mismatch in the coefficients of thermal expansion (CTE) of the integrated materials. Typically, the CTE of the silicon chip 12 is about 2.7 ppm/° C. and the CTE of the plastic substrate 18 is about 17 ppm/° C. Because the silicon chip 12 and the plastic substrate 18 have different coefficients of thermal expansion, a variation of ambient temperature deforms the package, and moreover, the products may fail. It has been known that the periphery region of the chip 12 is a highly thermal-stressed region.
To reduce the thermal stress, current practice includes adjustment of CTE and/or glass transformation temperature (Tg) of the underfill layer 20. However, a trade-off between the reduction of thermal stress and the protection of low-k dielectrics in the silicon chip 10 has to be taken into consideration. Further, the modification of the CTE or glass transformation temperature (Tg) of the underfill layer 20 is very complicated.